Advanced Ferroelectric Field Effect Transistors for Memory and AI Applications

In the past decades, the demand for high-performance large-capacity memory technologies has been arisen quickly due to the rapid growth of data generation. To address this challenge, researchers and engineers are actively exploring emerging memory devices and novel architectures, to overcome "the memory wall" problem. Among these, ferroelectric field effect transistors (FeFETs) have gained significant attention as a promising candidate for large-capacity high-performance storage and compute-in-memory. Hf0.5Zr0.5O2 based FeFETs offer substantial advantages, including energy efficiency, long retention, and fast operating speed. Moreover, the well-established high-k HfO2 fabrication technology and low operating voltage make Hf0.5Zr0.5O2 based FeFETs highly compatible with existing CMOS manufacturing processes, facilitating their integration into next-generation memory and computing systems. In this report, a FeFET process integration flow is proposed. Layout design, fabrication techniques, and device characterizations are discussed. Applications in secure storage, compute-in-memory, spatial-temporal sequence detection are experimentally demonstrated. To enhance the memory window and achieve multi-level storage, a charge-trapping layer is introduced onto the ferroelectric layer to induce gate-side injection. Various configurations of the charge-trapping layers are investigated to compare their performance. Large-memory-window FeFETs are experimentally demonstrated. Read/pass disturb is one of the main challenges FeFETs are facing when used as a storage solution. Long-term stress applied to FeFETs can disturb the high-VTH state, leading to data loss. The origin of the read disturb issue is explored by analyzing the correlations between the external electric field and internal ferroelectric polarization. Solutions for the pass disturb-free operations are also proposed and experimentally validated. Finally, future work is outlined to guide further exploration. A double-gate, pass disturb-free, large-memory-window FeFET for vertical NAND storage is presented, along with detailed designs and feasibility studies. Current progress on the device fabrication and characterizations are also reported.