Application-Driven Cross-Layer Design and Benchmarking with Emerging Devices

Data movement and processing have become significant bottlenecks for conventional Von Neumann architectures, especially as dataset sizes continue to grow. This issue is particularly concerning for deep learning deployment in Internet-of-Things (IoT) devices, which typically require real-time processing and power efficiency while being constrained by limited power and computational resources. Researchers have extensively explored solutions to reduce data movement and address the memory wall problem using complementary-metal-oxide-semiconductor (CMOS) technology. However, the limitations of CMOS technology in designing fast and dense on-chip memories, coupled with the intrinsic penalty of moving large volumes of data between memory and processor in Von Neumann architectures, underscore the need for new solutions. Computing in memory (CiM) is an emerging technique that can help alleviate the memory wall by eliminating data transfer (from memory to processor) and performing computation directly within the memory. Emerging technologies are of particular interest for realizing CiM architectures due to their non-volatility, unique behaviors that enable the design of customized circuits, and compatibility with CMOS technology. These emerging devices can be leveraged in various ways, including CiM cores for few-shot learning and hyper-dimensional computing, embedded memories for deep neural networks (DNNs) and graph analytics, and preventing side-channel attacks (SCA) in IoT devices. Furthermore, it is crucial to consider cross-layer solutions to explore the design space across different layers of the device hierarchy, i.e., device, circuit, architecture, and application. Each layer must be carefully examined through both bottom-up and top-down approaches. In this dissertation, I adopt a cross-layer approach to propose and evaluate CiM solutions for various applications. I further quantify the benefits of each design by benchmarking the developed circuits and architectures.