Adiabatic Clocking Circuit

The power consumption of electronic systems is constantly increasing due to the increase in the number of transistors per unit area caused by the shrinking of computer chip size, and consequently the heat generated. This is leading designers to consider other methods of reducing the production of heat. Traditional CMOS discards energy during each switching event in the form of heat to the surrounding environment. To reduce this loss of energy, a new approach must be taken which will allow the system to reuse this energy without dissipating it as heat to the system. This thesis will examine the clock generator chips that will create both positive and negative clocks for an adiabatic MIPS microprocessor. This clocking chip, while not adiabatic, will provide the control mechanism for the energy that is provided to the MIPS microprocessor as well as the retrieval of energy from the microprocessor. This thesis will describe the clocking circuit’s ability to recover energy that is lost in traditional CMOS logic through adiabatic reversible logic. The adiabatic reversible logic is implemented using Split-rail Charge Recovery Logic. The results will demonstrate that the clocking circuit is a viable alternative to traditional methods of computation that will allow for energy recovery while still processing instructions at a high rate.