Clock Line and Field-Coupled Input for Nanomagnet Logic

Nanomagnet Logic (NML) has received attention in recent years as it has the potential to replace or supplement the current CMOS technology. Benefits of NML include low power operation, non-volatility and radiation-hardness. Prior to this work, key components of NML architecture have been demonstrated experimentally with an on-chip clocking scheme, where the inputs were set with hard-coded horizontal or slanted nanomagnets. However, the clocking scheme needs further optimization. Also, an electronic control of the input magnets is essential to realize an interface between NML and CMOS systems.

In this work, the previously demonstrated on-chip clock line geometry was studied through simulation to obtain an optimum design in terms of efficient field generation. The generated field magnitudes estimated from magnetostatic simulations were related to the switching fields of nanomagnets using relevant experiments.

We also report the experimental demonstration of a field-coupled input scheme that can serve as an interface with an electronic system, and offers benefits such as low power operation and ease of fabrication with the existing on-chip clocking scheme. The programmability of such inputs allows us to test the same NML device for all possible input combinations. This concept was demonstrated for a slant-based OR gate and an NML wire. This electronic, field-coupled input integrated with the on-chip clocking is necessary for the realization of an integrated NML system.