Control and Dataflow in 28 nm CMOS for a FeFET-Based Compute-in-Memory Tensor Algebra Accelerator

This thesis presents a design for a digital control and dataflow system in 28 nm CMOS supporting a FeFET-based Compute-in-Memory (CIM) core designed by the Intelligent Microsystems Lab (IMSL) at the University of Notre Dame. This design includes a circuit for per-ADC asynchronous capture and forwarding of CIM outputs, a re-configurable adder tree taking advantage of the naturally ternary FeFET array weights, a memory system which uses banking and shift-registers to interface at high-bandwidth to the CIM array, and an abstracted programming interface suitable for further exploration of accelerator-algorithm co-design. An overview of the IMSL FeFET CIM chip architecture is provided for background, and the control and dataflow circuitry is described in detail. Design decisions and tradeoffs, as well as performance and power projections, and comparisons to related works, are discussed. This thesis proposes that a simple custom digital control system and a banked-memory-based dataflow and be effectively combined with a CIM array to exploit the unique architectural advantages offered by CIM.