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Electronic Noise in Graphene FETs

thesis
posted on 2011-12-08, 00:00 authored by Nan Sun
This thesis presents work on the low-frequency noise characteristics of FET structures made from single-layer graphene. Samples were created using standard e-beam lithography and exfoliated, epitaxially-grown, and CVD-grown graphene films. Noise measurements were made under vacuum at room temperature. The lowest overall noise was observed in epitaxially-grown films on SiC. We also investigated the gate dependence of the noise amplitude. In our experiment, a single noise peak was observed, offset from the charge neutrality point (CNP). A new noise model based upon a random array of charge traps is presented, which not only reproduces the observed gate voltage offset of the noise peak from the CNP, but also explains the noise asymmetry between the electron and hole branches.

History

Date Modified

2017-06-02

Defense Date

2011-11-30

Research Director(s)

Steven T. Ruggiero

Committee Members

H. Gordon Berry Steven T. Ruggiero Morten Eskildsen Malgorzata Dobrowolska-Furdyna

Degree

  • Doctor of Philosophy

Degree Level

  • Doctoral Dissertation

Language

  • English

Alternate Identifier

etd-12082011-173800

Publisher

University of Notre Dame

Additional Groups

  • Physics

Program Name

  • Physics

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