Estimation of Performance and Power of SIMD Processors

The concept phase of microprocessor design involves optimizations at all levels of the design, including the microarchitectural level, instruction set, and compiler. To evaluate ISA-level or microarchitecture modifications, the compiler also needs to be updated to take advantage of the new target. The requirement of meeting the power budget further complicates the problem. Given the size of the search space, it is unrealistic to use detailed modeling of the performance and power, because it requires a substantial amount of time to evaluate just a single point in the search space. However, such detailed analysis is not necessary in the early stages of a processor design. Instead, it is important to evaluate as many architectural ideas as possible, even with lower accuracy. My work develops an infrastructure for quicker exploration the microarchitecture- ISA-compiler design space using estimation. A benchmark is first profiled on a host machine, then the assembly code of the compiled benchmark is scheduled on the target processor, and the profile information is used to produce an estimate of performance and power. This approach is applicable to general purpose processors, but specifically targets SIMD processors. A retargetable SIMDization phase was developed, which is capable of generating SIMD instructions, including data reordering instructions, or permutations. The SIMDization phase was validated on hardware (Pentium), and the estimation methodology was validated against commonly used modeling tools (SimpleScalar and Wattch).