Gallium Nitride Field-Effect Transistors for Low-Power Applications

For applications in ultra-scaled integrated circuits (ICs) and future Internet of Things (IoT), digital and high-speed analog devices capable of low power operation are needed. In this work, two types of novel gallium nitride (GaN) transistors promising for these low power applications­­­-- GaN nanowire MOSFETs and GaN/InN/GaN tunnel field-effect transistors (TFETs)-- are explored both theoretically and experimentally.

Nanowire MOSFETs are promising for more aggressive scaling, high-frequency operation at reduced power, and sensing applications. By combining these features with the intrinsic material properties of GaN, such as high electron mobility and wide band gap, GaN nanowire MOSFETs appear promising for the low-power high-speed applications and sensors. In this work, Al₂O₃/GaN MOS structures fabricated using atomic-layer-deposition (ALD) are first investigated to study the oxide/semiconductor interface. Using this optimized ALD process, fabricated GaN nanowire MOSFETs exhibit promising device performance metrics, including an average switching slope (SS) of 61 mV/dec over 4 decades of drain current, and an on-current (I_ON) of 44 mA/mm. To improve the process controllability and enable ultra-dense integration, vertical GaN nanowire MOSFETs may be preferred, a fabrication process flow for which is presented.

TFETs are being explored for low-power logic. Using quantum-mechanical tunneling instead of thermionic emission, TFETs have the potential to achieve SS below 60 mV/decade. TFETs based on small band gap materials, such as III-V materials, tend to exhibit large off-currents and typically suffer from ambipolar conduction. To address these challenges, wide band gap III-nitride based TFETs are explored in this work. These devices use polarization engineering to overcome the difficulty of tunneling inefficiency imposed by wide band gap. An analytical model for GaN/InGaN/GaN tunnel junctions have been developed. GaN/In_0.22Ga_0.78N/GaN diodes have been fabricated and characterized, and simulation-based exploration of the design space for III-nitride based TFETs has been performed. Simulations suggest that achieving on/off ratios exceeding 10⁶, as well as SS well below the 60 mV/dec and I_ON on the order of 100's of mA/mm should be possible. This level of performance projects energy-delay products approaching 67 aJ*ps/um, a value well beyond projections for conventional CMOS. Fabrication options and the prospects for additional applications are also evaluated.