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Low Power Bistable-Body Tunnel SRAM

thesis
posted on 2009-12-11, 00:00 authored by Kamal M Karda
A bistable-body tunnel SRAM is proposed and validated using simulations. This cell, using one transistor and two tunnel diodes, is a high speed, low power static memory cell, offering over four orders of magnitude reduction in static power compared to 6T SRAM at the 32 nm technology node. The speed of the cell is comparable to the 6T SRAM. A layout with cell area equal to 48 F2 is shown. A two-transistor based negative-differential -resistance element is analyzed as an alternative to tunnel diode in bistable-body Tunnel SRAM. The peak to valley ratio of 2000 is obtained for the two-transistor based NDR element at the 32 nm transistor technology node.

History

Date Modified

2017-06-05

Research Director(s)

Jay Brockman

Committee Members

Debdeep Jena Wolfgong Porod

Degree

  • Master of Science in Electrical Engineering

Degree Level

  • Master's Thesis

Language

  • English

Alternate Identifier

etd-12112009-205409

Publisher

University of Notre Dame

Additional Groups

  • Electrical Engineering

Program Name

  • Electrical Engineering

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