Manufacturable Process for High Operating Temperature Silicon Single-Electron Transistors

CMOS has been the workhorse for the IC industry for past 3 decades and its enormous success is derived mainly from successive improvements in device scaling and the concomitant increase in device density and circuit complexity on a single chip. However, most observers agree that the CMOS scaling will end sometime between 2015 and 2019 due to several fundamental reasons, but perhaps the most important being the power density. Research has been seeking an alternative for conventional CMOS technology and one of the suggested devices is the single-electron transistor (SET). SETs are 3-terminal devices where the source-drain conduction is by a tunneling mechanism through a tiny island whose potential is controlled through a gate. At Notre Dame SETs are primarily used as an enabling device for the development of QCA (Quantum-dot Cellular Automata) architecture, which may be better suited for molecular nanoelectronics than more conventional approaches. Single electron devices typically need to operate at very low temperatures and also suffer from the problem of fluctuating background charges that randomly change the device behavior. Work done by other researchers has shown that Si based devices are less vulnerable to background charge offsets, and by utilizing techniques developed for VLSI technology one can make the Si devices dimensionally smaller and hence operate at room temperature and above. This dissertation reports the development and experimental realization of a novel fabrication technique using lithography, dry etching and chemical mechanical polishing (CMP) to manufacture Si-SETs with well-defined island and tunnel junctions. The device design incorporates the best working material (Si) with the most-studied insulator (silicon dioxide) for tunnel junctions in a CMOS compatible process flow. The reported Si-SETs are the first to be fabricated using our methodology and also the first to be thoroughly studied and with published results. The fabricated device showed Coulomb blockade oscillations above 150 K and the estimated charging energy was in excess of 20 meV. The stability of the device was studied by measuring the gate dependence of the source/drain conductance for over 19 hours at 77 K and showed very stable device behavior for the entire period with a charge offset of 0.04$e$. The deviation of the successful device from the intended design has been studied through experiments and analysis. Improvements to the fabrication scheme have been suggested to eliminate the problems encountered and improve the yield.