Nanomagnet Logic: From Devices to Architectures
Nanomagnet logic (NML) is an emerging device technology that exploits the magnetic state of nanoscale magnets to encode logic values. NML is being considered as a potential replacement for current charge-based technologies (namely, CMOS transistors) in order to achieve increased performance in terms of energy, delay, and/or area. The potential advantages of NML are: devices are non-volatile and radiation hard, device switching events consume little power, devices are scalable to the superparamagnetic limit, and there is a clear path to implementation that leverages current CMOS fabrication techniques. The goal of this work is to advance the state of the art for NML in order to realize these potential advantages at the application and architecture levels.
In order to evaluate the ultimate performance of NML, methods are needed to bridge the gaps between the device and circuit levels, and between the circuit and architecture and application levels. This dissertation thus considers methods to analyze NML device-to-device interactions that allow for the design of complex circuits. Next, this work considers the interaction between NML circuits and the clock required to re-evaluate the circuits. Specifically considered is how to model a proposed clock structure to determine its effects on NML circuit logical correctness, power, and energy requirements. Furthermore, this dissertation shows how uni-directional dataflow can be accomplished in the context of these realistic clock structures. This study of NML clocking allows for three studies at the architecture and application levels. First, this work shows how even with the energy consumed in the proposed clock, NML could outperform CMOS in terms of the energy delay product for a ripple carry adder benchmark. Second, this dissertation demonstrates how to realize non-volatility in NML in order to enable non-volatile NML shift registers with low energy operation. Finally, this work demonstrates how NML could fit into a stochastic computing architecture to provide performance improvements over conventional and stochastic CMOS equivalents.
History
Date Modified
2017-06-05Defense Date
2013-05-17Research Director(s)
Michael NiemierCommittee Members
X. Sharon Hu Gyorgy Csaba Wolfgang PorodDegree
- Doctor of Philosophy
Degree Level
- Doctoral Dissertation
Language
- English
Alternate Identifier
etd-07142013-222709Publisher
University of Notre DameProgram Name
- Computer Science and Engineering