Piezoflexure-enabled nanofabrication using translated stencil masks

In this study, piezoflexure-enabled nanofabrication (PEN), a new technique for forming nanometer-scale features based on the combination of dynamic stencil lithography and lift-off processing is analyzed, investigated, and demonstrated. In the PEN approach, a deposition substrate is translated under a stencil mask in an electron-beam evaporator between depositions of dissimilar materials. The piezoelectric translation defines the interembedded features that are later differentially etched to reveal the desired patterns. This technique is inherently clean, without resists, organics, and bakes. The masks are reconfigurable, since a single rectangular aperture mask can be used to batch fabricate a wide array of device structures in a single pump-down cycle of the evaporator. As a first part of this project, the PEN system was designed and constructed. A stencil mask fabrication technique based on anisotropic etching of silicon was developed and square apertures as small as 1 micron on a side with edge uniformity on the order of 10 nanometers were demonstrated. Several process attributes such as geometrical edge taper, mask clogging, thermal expansion due to radiative heat, and lateral material diffusion during deposition have been identified and characterized. The lateral spread of materials has been investigated in a series of experimental matrices enabled by the ability of the PEN system to perform multiple independent evaporations in the same run. The lateral diffusions were characterized by atomic force and scanning electron microscopy to show that material displacement under the stencil mask can range from approximately 0.1 to 2 µm even near room temperature (45 °C) with strong dependence on the deposited material and the vacuum conditions. It was shown that evaporation in N2 or O2 background pressure suppresses the spreading of Al, Cr, Pt, and Ti by slightly more than a factor of two. In order to explore and develop the capability of this novel technique several structures have been fabricated. Nanometer-scale wires with minimum feature dimension of approximately 30 nm and nanowire pairs with nanometer-scale spacings have been created. Arrays of Al/AlxOy/Ge metal-oxide-semiconductor (MOS) structures deposited with varying evaporation conditions have been formed for rapid material characterization. Finally, a poly-Ge channel thin film transistor structure was fabricated.