Tunnel Transistor Modeling

Tunneling field effect transistors (TFETs) have recently attracted considerable interest because of their potential use in low power logic applications. The major advantage of tunnel transistors is the possibility to achieve less than 60 mV/decade sub-threshold swing, which is the thermionic limit in conventional MOSFETs. In this work, simulation of III-V semiconductor based tunnel transistors has been explored using both commercially available simulator (Synopsys TCAD) and novel analytical compact models.

Synopsys TCAD was used to simulate InAs homo-junction TFET. For the purpose of obtaining higher device performance, the use of AlGaSb/InAs heterostructures was then explored. Contrary to expectations, it was observed that the simulation predicts dramatic changes in device performance as a function of AlGaSb composition.

In order to gain more physical insight, also to reduce computer simulation time, a compact model was built to simulate the tunnel transistors. Analytical expressions for the electrical potential in single-gate (SG), double-gate (DG) and gate-all-around (GAA) tunnel transistors have been derived. The model predicts that the GAA geometry is not always the best geometry when quantum confinement is included in the model.