Wideband Chip-to-Chip Interconnects for High Performance Computing

The fact that modern processors can utilize data faster than modern memory systems can supply it results in the 'processor-memory gap.' This disparity in supply and demand has been addressed with several approaches, primarily architectural. This research suggests that alternative packaging methods can improve system performance. This study designed, fabricated, and simulated performance to quantify Quilt Packaging (QP), a high speed chip-to-chip interconnect technology, within the context of 'embedded' system performance for comparison with several other approaches used or proposed in the high-performance computing (HPC) and embedded computing space. Initial exploration suggests that QP implementations of conventionally-packaged HPC nodes can result in improved performance through decreased latency and increased data throughput.