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  • Inventor(s):
    Gary H. Bernstein, Patrick Fay, Wolfgang Porod, Qing Liu
    Patent Number:
    US 7612443 B2
    Description:

    The present invention provides a quilt packaging system for microchip, a method for making such a quilt packaging system, microchips that may be used in a such a quilt packaging system, and methods for making such microchips.

    Date Issued:
    2009-11-03
    Resource Type
    Patent
  • Inventor(s):
    Michael Niemier, Mohammad T. Alam, Gary H. Bernstein, Xiaobo Sharon Hu, Wolfgang Porod
    Patent Number:
    US 8058906 B2
    Description:

    A non-majority magnetic logic gate device for use in constructing compact and power efficient logical magnetic arrays is presented. The non-majority magnetic logic gate device includes a substrate, symmetrically aligned magnetic islands (SAMIs), at least one misaligned magnetic island (MAMI), magnetic field inputs (MFIs), and at least one magnetic field output (MFO). The SAMIs and MAMI are electrically isolated from each other but are magnetically coupled to one another through their respecti…

    Date Issued:
    2011-11-15
    Resource Type
    Patent
  • Inventor(s):
    Gary H. Bernstein, Patrick Fay, Wolfgang Porod, Qing Liu
    Patent Number:
    US 8021965 B2
    Description:

    The present invention provides a quilt packaging system for microchip, a method for making such a quilt packaging system, microchips that may be used in a such a quilt packaging system, and methods for making such microchips.

    Date Issued:
    2011-09-20
    Resource Type
    Patent
  • Inventor(s):
    Wolfgang Porod, Gary H. Bernstein, Alexei Orlov, Gergo P. Szakmany
    Patent Number:
    US 9577173 B2
    Description:

    Nanoscale thermocouples are made of a single material and are shape-engineered to contain one or more variations in their width along their length. The mono-metallic nanowire junctions resulting from the width variation(s) exploit a difference in the Seebeck coefficient that is present at these size scales. Such devices have a wide variety of uses and can be coupled with an antenna in order to serve as an infrared detector.

    Date Issued:
    2017-02-21
    Resource Type
    Patent
  • Inventor(s):
    Douglas C. Hall, Scott Howard, Anthony Hoffman, Gary H. Bernstein, Jason M. Kulick
    Patent Number:
    US 9620473 B1
    Description:

    First and second integrated devices each have an optical component and a plurality of interconnect structures disposed one edge thereon. The first edge surface of the second integrated device is positioned contiguous to the first edge surface of the first integrated device. The interconnect structures disposed on the first integrated device are in physical contact with the interconnect structures disposed on the edge surface of the second integrated device so as to provide alignment for conve…

    Resource Type
    Patent
  • Inventor(s):
    Gary H. Bernstein, Patrick Fay, Wolfgang Porod, Qing Liu
    Patent Number:
    US 7608919 B2
    Description:

    The present invention provides a quilt packaging system for microchip, a method for making such a quilt packaging system, microchips that may be used in a such a quilt packaging system, and methods for making such microchips.

    Date Issued:
    2009-10-27
    Resource Type
    Patent
  • Inventor(s):
    Gary H. Bernstein, Patrick Fay, Wolfgang Porod, Qing Liu
    Patent Number:
    US 8623700 B2
    Description:

    The present invention provides a quilt packaging system for microchip, a method for making such a quilt packaging system, microchips that may be used in a such a quilt packaging system, and methods for making such microchips.

    Date Issued:
    2014-01-07
    Resource Type
    Patent
  • Inventor(s):
    Gary H. Bernstein, Patrick Fay, Wolfgang Porod, Qing Liu
    Patent Number:
    US 9633976 B1
    Description:

    A quilt packaging system includes a first and second electronic device each comprising a plurality of edge surfaces at least a first edge surface of which comprises one or more interconnect modules disposed thereon. The first edge surface of the second electronic device is positioned contiguous to the first edge surface of the first electronic device, and at least one of the one or more interconnect nodules disposed on the first edge surface of the first electronic device is configured to be …

    Date Issued:
    2017-04-25
    Resource Type
    Patent
  • Inventor(s):
    Douglas C. Hall, Anthony Hoffman, Scott Howard, Jason M. Kulick, Gary H. Bernstein
    Patent Number:
    US 10050027
    Description:

    First and second integrated devices each have an optical component and a plurality of interconnect structures disposed one edge thereon. The first edge surface of the second integrated device is positioned contiguous to the first edge surface of the first integrated device. The interconnect structures disposed on the first integrated device are in physical contact with the interconnect structures disposed on the edge surface of the second integrated device so as to provide alignment for conve…

    Date Issued:
    2018-08-14
    Resource Type
    Patent