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  • Inventor(s):
    Gary H. Bernstein, Patrick Fay, Wolfgang Porod, Qing Liu
    Patent Number:
    US 7612443 B2
    Description:

    The present invention provides a quilt packaging system for microchip, a method for making such a quilt packaging system, microchips that may be used in a such a quilt packaging system, and methods for making such microchips.

    Date Issued:
    2009-11-03
    Record Visibility:
    Public
    Resource Type
    Patent
  • Inventor(s):
    Gary H. Bernstein, Patrick Fay, Wolfgang Porod, Qing Liu
    Patent Number:
    US 8021965 B2
    Description:

    The present invention provides a quilt packaging system for microchip, a method for making such a quilt packaging system, microchips that may be used in a such a quilt packaging system, and methods for making such microchips.

    Date Issued:
    2011-09-20
    Record Visibility:
    Public
    Resource Type
    Patent
  • Inventor(s):
    Gary H. Bernstein, Patrick Fay, Wolfgang Porod, Qing Liu
    Patent Number:
    US 7608919 B2
    Description:

    The present invention provides a quilt packaging system for microchip, a method for making such a quilt packaging system, microchips that may be used in a such a quilt packaging system, and methods for making such microchips.

    Date Issued:
    2009-10-27
    Record Visibility:
    Public
    Resource Type
    Patent
  • Inventor(s):
    Gary H. Bernstein, Patrick Fay, Wolfgang Porod, Qing Liu
    Patent Number:
    US 8623700 B2
    Description:

    The present invention provides a quilt packaging system for microchip, a method for making such a quilt packaging system, microchips that may be used in a such a quilt packaging system, and methods for making such microchips.

    Date Issued:
    2014-01-07
    Record Visibility:
    Public
    Resource Type
    Patent
  • Inventor(s):
    Gary H. Bernstein, Patrick Fay, Wolfgang Porod, Qing Liu
    Patent Number:
    US 9633976 B1
    Description:

    A quilt packaging system includes a first and second electronic device each comprising a plurality of edge surfaces at least a first edge surface of which comprises one or more interconnect modules disposed thereon. The first edge surface of the second electronic device is positioned contiguous to the first edge surface of the first electronic device, and at least one of the one or more interconnect nodules disposed on the first edge surface of the first electronic device is configured to be …

    Date Issued:
    2017-04-25
    Record Visibility:
    Public
    Resource Type
    Patent