Development of Nanometer Ion Conductor for 2D-Crystal Memory and Universal Tunnel Transistor SPICE Model

A universal analytical TFET SPICE (Simulation Program with Integrated Circuit Emphasis) model has been developed to gain more insights into the benefits of TFETs in low power circuit applications and make performance projections. The model is valid in all four operating quadrants of TFETs. Based on the Kane-Sze formula for tunneling, this model captures the distinctive features of TFETs such as steep slope, superlinear onset, ambipolar conduction, and negative differential resistance. The TFET model has been validated on various TFET structures including a planar InAs double-gate TFET, an AlGaSb/InAs in-line TFET, and side-gate GaN/InN/GaN TFET, and good agreement is observed between the model and published simulations. To improve the accuracy of circuit simulation, more components have been added, in particular, a gate current model, a charge-based capacitance model, and a noise model. The model has been implemented in SPICE simulators using Verilog-A and implemented into native AIM-Spice, available on Mac, Windows, Android, and iOS.

Besides steep slope transistor models a further focus of this dissertation has been the exploration of new memory concepts. In particular a flash memory based on graphene and solid polymer electrolytes has been explored with the aim to provide nonvolatility, sub-volt access/program voltage, and low power consumption, but more importantly could provide nanosecond program/erase speed. Processes were developed for deposition of a 2D solid polymer electrolyte, 15-crown-5-ether-substituted cobalt(II) phthalocyanine (CoCrPc), the key enabling technology in the graphene flash memory. The 2D electrolyte was deposited by drop casting a CoCrPc-containing solution onto highly ordered pyrolytic graphite (HOPG) followed by Ar annealing. Atomic Force Microscopy (AFM) confirms that monolayer CoCrPc formation is achieved with a thickness of ~0.5 nm. To understand the basic physics of ion- electron double layers across an ion conductor with nanometer thickness, a simplified memory structure was proposed and subsequently fabricated and tested. Program tests demonstrate that the memory cell can be programmed and erased by applying positive and negative back gate biases. Besides memory, the 2D electrolyte can also serve as a reconfigurable ion gate for 2D semiconductors or a doping technique in 2D FETs and TFETs.