Design, Fault Studies, and Performance Analysis for Nanomagnet Logic PLAS and Other Nanomagnet Logic Architectures

In order to continue the performance and scaling trends that we have come to expect from Moore's Law, many emergent computational models, devices, and technologies are actively being studied to either replace or augment CMOS technology. Nanomagnet Logic (NML) is one such alternative. NML is a device architecture that utilizes the magnetization of nano-scale magnets to perform logical operations. NML has been experimentally demonstrated and operates at room temperature. We present an NML Programmable Logic Array (PLA) based on a previously proposed reprogrammable Quantum-dot Cellular Automata PLA design. We also discuss the fabrication and simulation validation of the circuit structures unique to the NML PLA. We present a fault model for NML PLAs, and provide an improved technique for mapping logic to the NML PLA. We present area, energy, and delay estimates for the NML PLA, compare the area of NML PLAs to other reprogrammable nanotechnologies, and analyze how architectural-level redundancy will affect performance and defect tolerance in NML PLAs. Because the nanomagnets are non-volatile, as data flows through a circuit, it is inherently pipelined. This feature makes NML an excellent fit for systolic architectures, which could enable low-power, high-throughput systems that can address a variety of application-level tasks. When considering possible NML systolic systems, the underlying systolic clocking scheme affects both architectural design and performance. We explore these issues in the context of two NML designs for simplified convolution, both of which focus on different dataflow patterns. We also study N-bit NML adders and multipliers in the context of high-throughput NML systems. We compare parallel and serial NML designs and compare NML to CMOS in terms of delay and energy. We also explore possible performance enhancement techniques for NML in an effort to make NML as low energy as possible.