Reversible Computing: The Design of an Adiabatic Microprocessor

Master's Thesis


Despite the exponential progress over the past fifty years the increase of performance of microprocessors has recently come to a rather abrupt end. Modern microprocessors are limited by heat dissipation. Speeds have been capped around 4 GHz since 2004 to limit heat generation. Such speeds are well below the RC time constant limit of the circuits, sacrificing speed to prevent the chips from melting. Reversible computing is a viable alternative to traditional circuit implementations since it reduces heat generation by avoiding unnecessary dissipation. Traditional CMOS circuits dissipate power on every switching in the form of heat. Adiabatic reversible computing uses reversible logic and quasi-adiabatic transitions to reduce heat generation by introducing a trade-off between speed and power. By using reversible logic and switching the circuits slowly, relative to their RC time constants, power can be dramatically reduced. In this thesis, I will present the design of a 16-bit adiabatic microprocessor that operates at 0.5 GHz dissipating an energy one order of magnitude lower than its CMOS counterpart.

The adiabatic microprocessor is a multicycle RISC processor with a 16-bit datapath and it follows the MIPS architecture. Only a subset of instructions is implemented but they are sufficient for universal computation. Adiabatic reversible logic is achieved using split-rail charge recovery logic (SCRL) with Bennett clocking, which consists of clocks that only ramp up once the previous stage has a valid steady state. An adiabatic SCRL implementation allows a circuit to operate both in adiabatic and in standard CMOS mode. The adiabatic microprocessor design includes on-chip temperature sensors that directly measure heat dissipation and provide a direct comparison of the power between the two modes of operation.

The 16-bit adiabatic microprocessor is successfully implemented in 90 nm technology with an operating frequency of 0.5 GHz, which demonstrates the design of a real-life circuit using adiabatic reversible logic and shows a promising future for energy-efficient computing.


Attribute NameValues
Author Rene Celis Cordova
Contributor Gregory L. Snider, Research Director
Contributor Alexei O. Orlov, Research Director
Degree Level Master's Thesis
Degree Discipline Electrical Engineering
Degree Name Master of Science in Electrical Engineering
Banner Code
  • MSEE

Defense Date
  • 2019-11-01

Submission Date 2019-11-19
Record Visibility and Access Public
Content License
  • All rights reserved

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