Clock Line Fabrication and Analysis for Nanomagnet Logic

Nanomagnet logic (NML) is a low power, nonvolatile, and radiation-hard technology that could supplement or possibly replace CMOS logic technologies. To further the study of NML technology, a reliable on-chip clocking scheme is required. In this thesis, we explore the fabrication steps required to build clock lines for NML. This damascene process utilizes chemical mechanical polishing (CMP) of copper. The process has proven to be reproducible and result in a high yield of reliable clock line chips. We also examine clock line analysis techniques, including characterization and simulation studies. The surface roughness analysis demonstrates that these clock lines are suitable for further NML processing. The simulations demonstrate that not only can the isolated clock lines can be used to clock NML circuits, but that we can build adjacent clock lines for data pipelining. Future research projects, which utilize CMP in NML, include building these adjacent clock line structures, and fabricating NML circuits using a nanodamascene process.