A Practical Design Methodology for an All-Digital Transmitter Architecture via Binary Sequence Search and a Look-Up Table Approach to Modulation

The relentless improvement in very large-scale integration (VLSI) technology over the past few years has made it feasible to conceive of an all-digital transmitter architecture that entails modulation as well as digital up-conversion to RF on a single DSP chip. However, shifting the RF stage to the digital domain severely burdens the dynamic range and bandwidth requirements of the high resolution DACs that provide the interface between the digital and the analog domains. The alternative is to use a1-bit DAC that operates on a binary DSP output that trades resolution in amplitude for resolution in time by quantizing a highly oversampled (e.g., by a factor of 100)time domain signal, for example, a converter. This, in turn, taxes the on-chip requirements. The number of floating point operations that need to be performed on the DSP per second grows linearly in the oversampling ratio, once again putting the transmitter design beyond the reach of DSP speeds for many years to come. This thesis presents a technology that overcomes the barriers of both DAC dynamic range and computational speed and presents a practicable scheme for building high-frequency direct-digitizing transmitters. The transmitter uses a simple look-up table to generate a binary stream, which then is filtered to produce a radiated signal so that there is no need for precise digital-to-analog converters. The data in the look-up table is produced by a new constrained list-decoding algorithm operating over the real alphabet. The transmitter can be a modulator only, or a combined encoder and modulator. The technology presented in this thesis supports generation of RF signals for commercial applications, e.g, 10 Gbit DSP architectures being produced for Ethernet can be directly used to transmit these binary sequences. This thesis presents spectra and error vector magnitude measurements for GMSK and BPSK signals with frequencies over 10 GHz for a wide range of data rates. When this all-digital transmitter structure is used in high-speed applications like Radar synthesizers, however, the output contains significant spurious signals that considerably degrade the spurious-free dynamic range (SFDR) at the DAC output.This is because when the output clock speed approaches the intrinsic bandwidth of the DAC, even a 1-bit DAC which intrinsically avoids static nonlinearities exhibits dynamic nonlinearity that causes past output symbols to interact in a nonlinear fashion with the present symbol. The second part of this thesis presents a simple and very general model for this nonlinear intersymbol interference (ISI) and uses it to design binary signals that can both measure and suppress the spurious tones that arise in a single-bit DAC. The experimental verification is presented in two phases of measurement for three different hardware setups. The first set of measurements establishes the presence of the spurious tones in the hardware, as predicted by the model, and the second set demonstrates improvements in SFDR of up to 22 dB after the suppression of the spurious tones. While the analysis in this thesis is for a 1-bitDAC, extension to multibit DACs is straightforward, since a multibit DAC is merely a collection of 1-bit DACs and exhibits the same nonlinear effects.