Fabrication of Deep-Submicron Complementary Metal-Oxide-Semiconductor Devices

The most commonly adopted method for building better Complementary Metal- Oxide-Semiconductor (CMOS) device is by reducing the physical dimensions of the structure. Through scaled size-reduction, CMOS devices can run at higher speed, consume less power and attain higher packing density. The aim of the thesis is to design the fabrication process for building CMOS devices with 0.25μm gate length and Quilt- Packaging protruding metal nodules. Alterations to the existing one-and-a-half micron CMOS fabrication process were made to accommodate the structural modification for the deep-submicron device. Prior to wafer processing, computer simulations were executed to determine the suitable processing conditions and to predict the electrical behavior of such device. Pattern definitions would be relied on a combination of photolithography and electron beam lithography. Although we are unable to complete the fabrication process at the moment, we have demonstrated the ability to perform the large-scale electron beam lithography needed for our fabrication with the Elionix ELS-7700 EBL system.