Design and Fabrication of Vertical Tunnel Transistors for Low-Power Logic Applications

Interband tunneling field effect transistors (TFETs) have come under intensive investigation for logic applications due to their promise for enabling low VDD operation because of their potential for achieving extremely low subthreshold swing. The work described here includes both experimental as well as theoretical contributions to the understanding of III-V based TFETs.

InGaAs/InP vertical tunnel FETs and tunnel diodes were first fabricated and characterized. NDR was observed in the tunnel diode I-V characteristics, indicating the InGaAs/InP junction was indeed a tunnel junction. InGaAs/InP vertical tunnel FETs with InGaAs airbridge were demonstrated in a process based on electron-beam lithography, and an on/off ratio of 800 was obtained experimentally at VD = 0.1 V. The on-state current of the fabricated InGaAs vertical TFET was relatively low compared with published results, primarily because the air-bridge structure used in this work has a much larger separation between the gate and drain contact, which results in a higher access resistance.

To further improve the on-state performance, vTFET based on the AlGaSb/InAs material system was explored by numerical TCAD simulation. Impact of geometric parameters on n-type vTFET performance were studied, including source doping, drain extension, drain undercut, gate length, and oxide thickness. A complementary p-type vTFET was also designed and optimized, which makes complimentary circuits possible. The DC and AC performance of single devices as well as complimentary circuits (logic inverters) as a function of fan-out loading have been investigated, showing that vTFET has the potential to replace CMOS technology for low power logic application in the future.