Low Power Bistable-Body Tunnel SRAM

A bistable-body tunnel SRAM is proposed and validated using simulations. This cell, using one transistor and two tunnel diodes, is a high speed, low power static memory cell, offering over four orders of magnitude reduction in static power compared to 6T SRAM at the 32 nm technology node. The speed of the cell is comparable to the 6T SRAM. A layout with cell area equal to 48 F2 is shown. A two-transistor based negative-differential -resistance element is analyzed as an alternative to tunnel diode in bistable-body Tunnel SRAM. The peak to valley ratio of 2000 is obtained for the two-transistor based NDR element at the 32 nm transistor technology node.