Since the turn of the century, the performance of CMOS processors has been constrained more by the thermal budget than device limitations because air cooling limits dissipated power density to about 100 W/cm2, and performance trade-offs must be made to meet cooling requirements. Dissipation constraints have limited CPU speeds to 3-4 GHz for most systems, and scaling supply voltage, the traditional method of keeping power dissipation within limits, has stalled because the necessary commensurate down scaling of the threshold voltage causes an exponential increase in leakage current due to the inherent subthreshold swing of 60 mV/dec of current in MOSFETs.
Much research has been devoted to steep devices to circumvent the passive power term and enable a lower VDD, but an alternative approach is quasi-adiabatic reversible computing, which uses adiabatic transitions and reversible logic designs to minimize the amount of heat dissipated, and break the direct link between the bit energy and dissipation. If a linear ramp is used to charge and discharge bits instead of abruptly connecting them to VDD or ground, then as long as the ramp time is longer than the RC time constant, the active power dissipation can be significantly lower than for conventional CMOS. It should be noted that cooling constraints already require speeds well below the RC cutoff.
This work describes quantitative measurement of the heat dissipation in an adiabatic reversible shift register and investigation of piezoelectric microelectromechanical (MEMS) resonators as possible clock sources for reversible logic. Using on-chip nano-thermocouples, the heat dissipation in the adiabatic reversible shift register is measured and analyzed for reversible and irreversible operating modes. It is observed that the reversible mode dissipates up to 82% less heat than the irreversible mode and that this value matches well with theory, suggesting that even greater improvements are possible. In pursuit of designing a complete and integrated adiabatic reversible processor, MEMS resonators as potential clock sources were also investigated and fabricated. The energy storage and linearity limitations of several resonator designs were analyzed and contour-mode AlN resonators were fabricated and characterized.