Quilt Packaging Integration and Fabrication of Deep-Submicron Complementary Metal-Oxide Semiconductor Devices

This thesis presents the development and progress at Notre Dame of a 0.25 Ì_å_m Complementary Metal Oxide-Semiconductor (CMOS) process that integrates a novel packaging process, Quilt-Packaging (QP). Deep-submicron lithography and Very Large Scale Integration (VLSI) circuit with roughly 50000 transistors per chip require the high through-put of the G-line photolithography stepper tool and the high-resolution of the Electron Beam Lithography (EBL) tool. An elaborate mix-matching scheme between the two very different tools provides accurate pattern placement to meet the stringent requirement for alignment. Process and device simulation were executed to tune the various process parameters and predict the electrical behavior of such devices. This CMOS process features 5nm gate oxide, various implants to suppress Short Channel Effects (SCE), dual-type polysilicon gates, silicon nitride spacer, titanium silicide, and two metal layers for interconnection. Copper nodules for Quilt Packaging (QP) are fabricated and protrude outside the chips to provide fast off-chip interconnection speed for the CMOS circuitry. Each die contains twelve individual QP chips that can be soldered together with another QP chips from the same wafer or another wafer with a different process, to achieve the ultimate high performance system integration.