Novel Silicon and Non-Silicon Transistors for Low Power Logic Applications

Doctoral Dissertation
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Abstract

The power constrained scaling of conventional Silicon Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) below the 90nm technology node has led to innovations such as strained-Si, strained SiGe, high-k/metal gate, FinFET, as well as mitigation of parasitic elements to enable improvement in device performance and lowering of cost-per-function of integrated circuits. Higher mobility channel materials for n and p channel transistors, channel architecture innovation and mitigation of device-to-device variation are focus of current research to further boost transistor performance at scaled technology nodes.

This dissertation focuses on three key aspects of enhancing transistor performance, mitigating variation, and improving reliability in CMOS transistors. In the first section, we evaluate and benchmark Gate-All-Around Nanowire FETs (GAA-NW) vs current FinFET architecture for 5nm technology node via TCAD finite element simulation and circuit level analysis. The concept of Electrically Gate-All-Around Hexagonal Nanowire FET (HexFET) is introduced to show that this channel architecture can provide electrostatic robustness similar to GAA-NW, in conjunction with the high current drive current capabilityof FinFET. Short channel experimental device results are in alignment with TCAD simulations.

In the second section, we focus on higher mobility compound semiconductor (III-V group materials) belonging tothe InxGa­1-xAs family as a potential channel material for high performance n-channel transistors. Weextend the HexFET concept to III-V FinFET architecture and show via TCAD simulation that high mobility quantum well InxGa­1-xAs FETs can outperform Silicon MOSFETsat the same technology node.. The third section of this thesis evaluates Oxygen-Inserted Silicon (OI-Silicon) channel MOSFETsto provide a cost-effective means for mobility improvement, gate leakage reduction, threshold voltage variation reduction and positive-temperature-bias-instability reliability improvement. OI Silicon is evaluated using Poly/SiO2 as well as HfO2 based high-K/Metal Gate stack, where we observe mobility improvement, gate leakage reduction and improved threshold voltage variation.

The dissertation concludes with a brief summary and a discussion of future work to further evaluate the device concepts portrayed in this work.

Attributes

Attribute NameValues
Author Jeffrey A. Smith
Contributor Christopher Hinkle, Committee Member
Contributor Suman Datta, Research Director
Contributor Alan Seabaugh, Committee Member
Contributor Patrick Fay, Committee Member
Degree Level Doctoral Dissertation
Degree Discipline Electrical Engineering
Degree Name Doctor of Philosophy
Banner Code
  • PHD-EE

Defense Date
  • 2020-10-29

Submission Date 2020-12-09
Record Visibility Public
Content License
  • All rights reserved

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