Voltage Scheduling Techniques for Dynamic Voltage Scaling Processors with Practical Limitations

Master's Thesis


Voltage scheduling is an essential technique used to exploit the benefit of dynamic voltage scaling processors. Though extensive research exists in this area, processor limitations such as transition overhead and voltage level discretization are not included simultaneously in any research processor model to date. Algorithms that account for individual limitations are not sufficient because some complications only emerge when limitations are considered simultaneously. We present two algorithms that yield valid results given an arbitrarily large transition time overhead. The first, LPEDF, offers a simple implementation, while the second, UAEDF, accounts for all three processor limitations to further reduce energy consumption.


Attribute NameValues
  • etd-03042004-140126

Author Bren Christopher Mochocki
Advisor Kevin Bowyer
Contributor Kevin Bowyer, Committee Member
Contributor Surendar Chandra, Committee Member
Degree Level Master's Thesis
Degree Discipline Computer Science and Engineering
Degree Name MSCSE
Defense Date
  • 2003-11-18

Submission Date 2004-03-04
  • United States of America

  • voltage scheduling

  • DVS

  • CAD

  • low power

  • embedded systems

  • University of Notre Dame

  • English

Record Visibility Public
Content License
  • All rights reserved

Departments and Units


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