Voltage scheduling is an essential technique used to exploit the benefit of dynamic voltage scaling processors. Though extensive research exists in this area, processor limitations such as transition overhead and voltage level discretization are not included simultaneously in any research processor model to date. Algorithms that account for individual limitations are not sufficient because some complications only emerge when limitations are considered simultaneously. We present two algorithms that yield valid results given an arbitrarily large transition time overhead. The first, LPEDF, offers a simple implementation, while the second, UAEDF, accounts for all three processor limitations to further reduce energy consumption.
|Author||Bren Christopher Mochocki|
|Contributor||Kevin Bowyer, Committee Member|
|Contributor||Surendar Chandra, Committee Member|
|Degree Level||Master's Thesis|
|Degree Discipline||Computer Science and Engineering|
|Departments and Units|