An interchip interconnection approach based on a new 2-D system-in-package (SiP) method?Quilt Packaging (QP), invented at the University of Notre Dame, is discussed. The principal idea of QP is to assemble a planar mosaic, or ?quilt,? of dies interconnected by conductive nodules that protrude from vertical faces of ICs. QP offers reduced delay, ultrawide bandwidth, low electrical noise, decreased system size and weight, and the opportunity for heterogeneous integration.
In this dissertation, modifications to previous QP fabrication processes are introduced. A new joining method for QP interconnection is presented, using solder paste applied with the pin transfer method, which greatly improves mechanical and thermal reliability, and manufacturability. Chip-to-chip alignment offsets smaller than 1 ?m are demonstrated. Simulations and measurements indicate that the microwave performance of QP interconnects provides ultrawide bandwidth. Moreover, the use of solder paste does not significantly degrade the microwave performance of QP. In particular, the return loss associated with the chip-to-chip QP nodules is better than 12.5 dB, and the insertion loss is better than 0.8 dB, at frequencies up to 110 GHz.
Mechanical and thermal reliability testing were performed on QP, including pull and thermal shock tests. A novel mechanical testing system that combines a force gauge and a micropull tester was designed and constructed. Pull tests were used to investigate the mechanical strength of QP, and it is found that individual nodules are about as strong as individual wirebonds, but acting together require several pounds of force to separate the chips.
Investigations were conducted to learn the effects of thermal shock on all components of the nodule system, including the inter-nodule solder, the copper nodule itself, and the nodule-to-substrate interface layers. Pull tests were performed after thermal shock testing, and it was found that during the first 200 thermal shock cycles, the pull force at failure drops significantly, but has little effect on the tensile strength of copper. The adhesion between copper and oxide is more vulnerable to thermal shock testing, and cracks were observed in the sidewall SiO2 isolation layer after thermal shock testing.