Fabrication of Metallic Single Electron Transistors Featuring Plasma Enhanced Atomic Layer Deposition of Tunnel Barriers

The continuing increase of the device density in integrated circuits (ICs) gives rise to the high level of power that is dissipated per unit area and consequently a high temperature in the circuits. Since temperature affects the performance and reliability of the circuits, minimization of the energy consumption in logic devices is now the center of attention. According to the International Technology Roadmaps for Semiconductors (ITRS), single electron transistors (SETs) hold the promise of achieving the lowest power of any known logic device, as low as 1×10⁻¹⁸ J per switching event. Moreover, SETs are the most sensitive electrometers to date, and are capable of detecting a fraction of an electron charge. Despite their low power consumption and high sensitivity for charge detection, room temperature operation of these devices is quite challenging mainly due to lithographical constraints in fabricating structures with the required dimensions of less than 10 nm. Silicon based SETs have been reported to operate at room temperature.

However, they all suffer from significant variation in batch-to-batch performance, low fabrication yield, and temperature-dependent tunnel barrier height.

In this project, we explored the fabrication of SETs featuring metal-insulator-metal (MIM) tunnel junctions. While Si-based SETs suffer from undesirable effect of dopants that result in irregularities in the device behavior, in metal-based SETs the device components (tunnel barrier, island, and the leads) are well-defined. Therefore, metal SETs are potentially more predictable in behavior, making them easier to incorporate into circuits, and easier to check against theoretical models.¹

Here, the proposed fabrication method takes advantage of unique properties of chemical mechanical polishing (CMP) and plasma enhanced atomic layer deposition (PEALD). Chemical mechanical polishing provides a path for tuning the dimensions of the tunnel junctions, surpassing the limits imposed by electron beam lithography and lift-off, while atomic layer deposition provides precise control over the thickness of the tunnel barrier and significantly increases the choices for barrier materials.

As described below in detail, the fabrication of ultra-thin (~1nm) tunnel transparent barriers with PEALD is in fact challenging; we demonstrate that in fabrication of SETs with PEALD to form the barrier in the Ni-insulator-Ni tunnel junctions, additional NiO layers are parasitically formed in the Ni layers that form the top and bottom electrodes of the tunnel junctions. The NiO on the bottom electrode is formed due to oxidizing effect of the O₂ plasma used in the PEALD process, while the NiO on the bottom of the top electrode is believed to form during the metal deposition due to oxygen-containing contaminants on the surface of the deposited tunnel barrier. We also show that due to the presence of these surface parasitic layers of NiO, the resistance of Ni-insulator-Ni tunnel junctions is drastically increased. Moreover, the transport mechanism is changed from quantum tunneling through the dielectric barrier to one consistent with the tunnel barrier in series with compound layers of NiO and possibly, NiSi_xO_y. The parasitic component in the tunnel junctions results in conduction freeze-out at low temperatures, deviation of junction parameters from ideal model, and excessive noise in the device. The reduction of NiO to Ni is therefore necessary to restore the metal-insulator-metal structure of the junctions. We have studied forming gas anneal as well as H₂ plasma treatment as techniques to reduce the NiO layers that are parasitically formed in the junctions. Using either of these two techniques, we reduced the NiO formed on the island after being covered with the PEALD dielectric and before defining the top source and drain. Later, the NiO formed on the bottom of the source/drain is reduced during a second reducing step after the source/drain are formed on the tunnel barrier. Electrical characterization of SETs that are made with the proposed reducing treatments enable us to study the effect of each reducing process on the properties of the constituent tunnel junctions. In comparison to the junctions annealed twice in forming gas at 400°C, we consistently observed a ~10× higher conductance in devices treated twice with H₂ plasma at 300°C. The possible damage to the barrier during the plasma treatment and thermally induced film deformation during the anneal which respectively, is believed to increase and lower the conductance are among the possible cause of this difference. Although both types of treatments were effective in alleviating the effect of the activated components in the junctions, all the devices that were treated by two anneal steps or by two H₂ plasma steps (for reducing the top and bottom NiO) show deviations from ideal simulated MIM SET model and suffer from significant random telegraph signal (RTS) noise. However, our results show that by using forming gas anneal for bottom NiO reduction and H₂ plasma for the top NiO reduction, one can achieve devices close to ideal MIM SETs with significantly less noise.