Cryogenic CMOS Technology and Monolithic-3D Integration for High Performance Computing

The relentless scaling of CMOS integrated circuit (IC) technology following Moore’s law has enabled faster, smaller, and energy efficient electronics for last 60 years. However, Moore’s Law has been predicted to face extreme challenges to meet the future requirements of seamless interaction between big-data oriented compute intensive domain in server-class systems and instant data centric memory intensive spaces in clients (autonomous vehicle, Internet-of-things systems, mobile computing etc.). In order to address these challenges in future computing systems, this thesis work focuses on novel design space exploration of CMOS technology by investigating: (a) Cryogenic-CMOS logic and memory technology for achieving extremely-high performance and energy efficiency in compute intensive application space, and (b) Monolithic three-dimensional (M-3D) integration of high-performance amorphous oxide semiconductor (AOS) transistors for high-capacity and high bandwidth embedded memory in memory intensive application space. Deeply scaled cryogenic-CMOS harnesses operating temperature as the primary knob to achieve ultimate energy-delay-product (EDP) performance limit. This thesis work investigates the potential of low temperature enabled performance boosters in 14nm FinFET platform through electrical characterization, compact model development and benchmarking EDP benefits of cryogenic CMOS. Low temperature enabled Equivalent Oxide Thickness (EOT) scaling is proposed for the first time, to potentially enable 0.2V logic operation and gain further 50% EDP improvement in cryogenic CMOS. A Novel gate-stack with aggressively scaled Zr-doped HfO₂ mixed-phase higher-κ gate-dielectric is proposed to meet the ultra-low EOT goal. Moreover, high-capacity, high-bandwidth and pseudo-static 1T Floating body RAM (FBRAM) with record ultra-fast write speed (~5ns) is demonstrated for the first time at cryogenic temperature for cache memory to provide potential advantage in core-to-cache balance, cache miss rate and power consumption. M-3D integration of back-end-of-the-line (BEOL) memory in a multitier structure aimed to increase memory capacity and inter-tier via density, resulting in an overall gain in memory bandwidth. In that context, this thesis also focuses on fabrication and characterization of BEOL compatible AOS channel (W-doped Indium-Oxide or IWO) FETs. Dual-gated IWO transistors with scaled channel length (50nm) and excellent switching characteristics is successfully demonstrated. Furthermore, mitigation of stoichiometric defects in amorphous oxide channel is also investigated through anneal treatments to improve device reliability of Oxide-Semiconductor FETs.