Tunnel Field-Effect Transistors: Device Models and Experiments on Two-Dimensional Semiconductors, Including Demonstration of Electric-Double-Layer Esaki Junctions

Doctoral Dissertation

Abstract

Supply voltage scaling, as a means of reducing power dissipation in integrated circuits, is hampered by the 60 mV/decade limit on the inverse subthreshold slope (SS) imposed by Boltzmann’s tyranny in today’s complementary metal oxide semiconductor (CMOS) transistors. For this reason, tunnel field-effect transistors (TFETs) are actively being investigated as CMOS alternatives for low-voltage applications thanks to their ability to achieve subthermal SS, i.e. below 60 mV/dec. Owing to their atomically thin body and transport attributes, transition metal dichalcogenides (TMDs) represent an intriguing class of channel materials for the realization of 2D TFETs. However, processing techniques suitable for the very-large-scale integration (VLSI) of TMD devices are still in their infancy.

As part of a TMD-based TFET process development on a silicon platform, some technology challenges such as a robust doping technique for tunnel junction formation, need to be addressed. As a first step, transport properties of molecular beam epitaxy (MBE) WSe2 films grown on amorphous oxides on Si are evaluated and benchmarked. To properly characterize the transport properties of MBE-grown WSe2 thin films in a FET configuration in the presence of Schottky barrier-limited injection at the contacts, a semianalytical model has been developed and validated against experiments for different TMD channel materials.

Ion doping employing the solid polymer polyethylene oxide:cesium perchlorate (PEO:CsClO4) is then applied to decanometer WSe2 channels to form 2D lateral Esaki junctions. This was achieved thanks to a proper electrostatic design of the strength and spatial extent of the electric double layers (EDLs) at the semiconductor/solid polymer interface as guided by numerical simulations.

Finally, the occurrence of hysteretic steep swings, SS < 60 mV/dec, employing a PEO:CsClO4 ionic gate on top of a WSe2 channel, required the analysis of transient phenomena associated with the formation and subsequent dissipation of EDLs at the electrolyte/semiconductor interface. We show that hysteretic steep SS can arise simply by the presence of a delay element embedded within the gate of a MOSFET. It is then the choice of measurement slew rate (SR) and slew direction that directly affects the measured SS.

Attributes

Attribute NameValues
Author Paolo Paletti
Contributor Alan C. Seabaugh, Research Director
Degree Level Doctoral Dissertation
Degree Discipline Electrical Engineering
Degree Name Doctor of Philosophy
Banner Code
  • PHD-EE

Defense Date
  • 2019-11-21

Submission Date 2019-12-02
Record Visibility Public
Content License
  • All rights reserved

Departments and Units
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