Optimizing the Internal Microarchitecture and ISA of a Traveling Thread PIM System

Heterogeneity, multiple on-chip processing elements, multithreading, intelligent caching mechanisms, and compiler-assisted thread-level speculation are a few of the features of emerging architectures for meeting the increasing performance demands and power constraints of future processors and workloads. In the design of future processors, two primary challenges facing computer architects are the overcoming of the memory wall and energy consumption reduction. To address these challenges, this work employs an iterative design methodology in the optimization of an innovative processor architecture that leverages the above features in the implementation of an advanced, powerful execution model called traveling threads for exploiting parallelism and data locality in tandem at multiple levels of granularity. The design of this Passive/Active Multicore (PAM) architecture and the development of mechanisms for locality-cognizant extraction of traveling threads offer insights into the benefits of utilizing computational migration at a granularity of parallelism between the conventional instruction and thread levels. Through these insights, we conclude that PAM and traveling threads are particularly well-suited for the joint exploitation of parallelism and data locality. Quantitative results support this conclusion, illustrating the architecture's significant potential improvements over those currently in use in terms of both execution time and energy consumption for standard benchmarks and scientific workloads.