Electronic Noise in Graphene FETs

This thesis presents work on the low-frequency noise characteristics of FET structures made from single-layer graphene. Samples were created using standard e-beam lithography and exfoliated, epitaxially-grown, and CVD-grown graphene films. Noise measurements were made under vacuum at room temperature. The lowest overall noise was observed in epitaxially-grown films on SiC. We also investigated the gate dependence of the noise amplitude. In our experiment, a single noise peak was observed, offset from the charge neutrality point (CNP). A new noise model based upon a random array of charge traps is presented, which not only reproduces the observed gate voltage offset of the noise peak from the CNP, but also explains the noise asymmetry between the electron and hole branches.