Power dissipation is one of the most challenging factors for continued semiconductor transistor scaling in the evolution of integrated circuits. The heat generation due to large power dissipation density restricts the device scaling in integrated circuits (ICs). To circumvent this power crisis in ICs, it requires exploring new device structures and operating principles. The goal is to design transistor switch in a way that the device dissipates less power during logic operation than conventional FETs, BJTs. To meet this requirement, it has been suggested to reduce the subthreshold slope of a transistor below the room temperature Boltzmann limit of 60 mV/decade. Here, we propose and analyze two methods for the reduction of energy dissipation in logic applications. The first is a steep subthreshold slope (< 60 mV/decade) transistor using a piezoelectric gate barrier for low-power switching. The second is a reduction of energy dissipation based on energy-conserving resonant switching in conventional circuits/systems.
In particular, we propose a novel method for realizing a steep transistor switch using the negative differential capacitance (NDC) of a compliant piezoelectric gate barrier. This effect exploits electric field induced electrostriction when nanoscale piezoelectrics are used as the active gate barriers of transistors. Electrostriction leads to a modulation of layer thickness under the application of voltage across the piezoelectric layer. Piezoelectricity and electrostriction in a piezoelectric barrier combine to provide negative differential capacitance (NDC) with internal charge amplification. The effect of the NDC in the gate capacitor of a FET is to boost the on-current, and to provide an opportunity for switching steeper than the 60 mV/decade Boltzmann limit. To show this effect, we first physically analyze and quantitatively develop the electromechanical piezoelectric capacitor using the Gauss’ law electrostatics. Owing to this physical mechanism, we show that there are regimes in the charge-vs.-voltage characteristics of piezoelectric capacitor where the capacitance becomes negative. By porting the negative capacitance of a piezoelectric barrier in the gate capacitor of a transistor, the total gate capacitance is expected to be enhanced as a result of piezoelectric charge amplification. This enhanced gate capacitance leads to a boost in the ON-current of the transistor. Also by exploiting the negative capacitance of a highly compliant piezoelectric barrier in the subthreshold regime of a transistor, the sub-threshold slope (SS) could possibly be reduced below 60 mV/decade of the transistor. To design the transistor switch, we quantitatively analyze carrier transport properties based on different scattering mechanisms in various semiconductor channel materials such as III-V semiconductors, and heterostructures. We also developed compact models for III-nitride HEMTs incorporating polarization charge to calculate transistor characteristics, and device parameters.
Using the transistor switches, we investigate and analyze energy dissipation in conventional CMOS circuits/systems. Finally, we propose a mechanism for the reduction of energy dissipation based on energy-recovery resonant switching by conserving energy in the circuit/system. In this approach, the dissipated energy to heat at each switching event is recovered through the controlled resonant switching and stored in an energy-recovery storage capacitor for later use in logic computation. This proposed mechanism in circuits is useful for developing energy-efficient systems such as low-power clocking, driving in large-area displays, and interfacing circuitry etc.
The work presented here would help to design low-voltage/low-power transistor switches, and also to design the energy-efficient computing circuits/systems.