Systems and methods for inter-chip communication

Patent

Description

A quilt packaging system includes a first and second electronic device each comprising a plurality of edge surfaces at least a first edge surface of which comprises one or more interconnect modules disposed thereon. The first edge surface of the second electronic device is positioned contiguous to the first edge surface of the first electronic device, and at least one of the one or more interconnect nodules disposed on the first edge surface of the first electronic device is configured to be in physical contact with at least one of the one or more interconnect nodules disposed on the first edge surface of second electronic device so as to provide an electrical connection between the first and second electronic devices at the first edge surfaces of the first and second electronic device.

Attributes

Attribute NameValues
Title
  • Systems and methods for inter-chip communication

Patent Number
  • US 9633976 B1

USPTO Link
Inventor
  • Gary H. Bernstein

  • Patrick Fay

  • Wolfgang Porod

  • Qing Liu

Inventor From Local Institution
  • Gary H. Bernstein

  • Patrick Fay

  • Wolfgang Porod

  • Qing Liu

Other Application
  • 14/090,993

Claims
  • 18

Cooperative Patent Classification codes
  • H01L 25/0655 (20130101); H01L 24/67 (20130101)

International Patent Classification codes
  • H01L 25/00 (20060101); H01L 25/065 (20060101); H01L 23/00 (20060101)

Language
  • English

Date Issued
  • 2017-04-25

Publisher
  • U.S. Patent and Trademark Office

Assignee
  • University of Notre Dame du Lac

Record Visibility Public
Content License
  • All rights reserved

Departments and Units
Member of

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