Design and Implementation of an FPGA-Based Image Processor: Exploring a Distributed Data Multi-Core Co-Processor Architecture

Master's Thesis


This thesis explores using a hybrid processing approach for doing application specific memory intensive processing. The hybrid system uses a general purpose processor (GPP) in conjunction with an FPGA-based Image Processor (FIMP) to improve performance for image processing applications. The hybrid architecture is designed to implement an image registration algorithm that partitions the algorithm into separate functions executing either on the GPP or the FIMP system. This thesis explores the trade-offs of different configurations for FIMP architecture, utilizing the flexibility of reconfigurable hardware to achieve maximum performance.

The FIMP system was designed in Verilog HDL and implemented on the Xtremedata XD1000 system, which uses an Opteron main processor and an Altera Stratix II FPGA co-processor. Multi-core systems of up to 32 nodes were implemented, using three network topologies: a bus, a ring and a fully connected mesh. Benchmark results for the FIMP system are compared to software execution. For an image registration algorithm using 256x256 gray scale images use of a 16 node fully connected FIMP system as a co-processor produced a 1.65 times speedup over the GPP alone.


Attribute NameValues
  • etd-07212009-135252

Author Daniel Govinda Rinzler
Advisor Dr. Jay Brockman
Contributor Dr. Jay Brockman, Committee Chair
Contributor Dr. Gary Bernstein, Committee Member
Contributor Dr. Ken Sauer, Committee Member
Contributor Dr. Patrick Flynn, Committee Member
Degree Level Master's Thesis
Degree Discipline Computer Science and Engineering
Degree Name MSCSE
Defense Date
  • 2009-07-17

Submission Date 2009-07-21
  • United States of America

  • co-processor

  • FPGA

  • image processing

  • image registration

  • University of Notre Dame

  • English

Record Visibility Public
Content License
  • All rights reserved

Departments and Units


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