Sc has been employed as an electron contact to a number of two-dimensional (2D) materials (e.g. MoS2, black phosphorous) and has enabled, at times, the lowest electron contact resistance. However, the extremely reactive nature of Sc leads to stringent processing requirements and metastable device performance with no true understanding of how to achieve consistent, high-performance Sc contacts. In this work, WSe2 transistors with impressive subthreshold slope (109 mV dec−1) and I ON/I OFF (106) are demonstrated without post-metallization processing by depositing Sc contacts in ultra-high vacuum (UHV) at room temperature (RT). The lowest electron Schottky barrier height (SBH) is achieved by mildly oxidizing the WSe2 in situ before metallization, which minimizes subsequent reactions between Sc and WSe2. Post metallization anneals in reducing environments (UHV, forming gas) degrade the I ON/I OFF by ~103 and increase the subthreshold slope by a factor of 10. X-ray photoelectron spectroscopy indicates the anneals increase the electron SBH by 0.4–0.5 eV and correspondingly convert 100% of the deposited Sc contacts to intermetallic or scandium oxide. Raman spectroscopy and scanning transmission electron microscopy highlight the highly exothermic reactions between Sc and WSe2, which consume at least one layer RT and at least three layers after the 400 °C anneals. The observed layer consumption necessitates multiple sacrificial WSe2 layers during fabrication. Scanning tunneling microscopy/spectroscopy elucidate the enhanced local density of states below the WSe2 Fermi level around individual Sc atoms in the WSe2 lattice, which directly connects the scandium selenide intermetallic with the unexpectedly large electron SBH. The interface chemistry and structural properties are correlated with Sc–WSe2 transistor and diode performance. The recommended combination of processing conditions and steps is provided to facilitate consistent Sc contacts to WSe2.
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