Microwave Performance and Fabrication Of Quilt Packaging, a Novel Chip-To-Chip Interconnect Technology

Microelectronics packaging forms the link between the nanometer scale transistors on a chip and the micrometer or millimeter scale interconnects that provide electrical connections between chips and other circuit components. For modern digital systems, the number of interconnects is small compared to the number of active devices on the chip, and given the high data processing throughput of many modern systems, the interconnects are by necessity shared or multiplexed. For systems with high data throughput multiplexed through a limited number of interconnects, conventional approaches such as wire bonds and flip-chip interconnects may not offer sufficient signal integrity and bandwidth to handle the required data rates. Interconnect bandwidth and frequency limitations apply to millimeter-wave analog systems as well; the ability to process signals in the millimeter-wave and THz frequency regimes are becoming increasingly important for emerging applications in communications, security, and scientific research. For such millimeter-wave systems, the bandwidth of individual interconnects is paramount, and the packing densities are far less important.

To address these limitations for both digital and analog systems, a direct-coupled chip-to-chip interconnect technology called 'quilt packaging' is explored. This technology is based on micro-electro-mechanical system (MEMS) inspired fabrication processing. Quilt packaging uses copper projections called 'nodules' to bridge a short air gap between one chip and the next. It is shown experimentally that this technology can directly address interconnect data rate limitations, offering measured insertion losses below 1.4 dB and return losses of better than 12.5 dB from DC to 220 GHz with well-controlled latency and phase. Furthermore, simulations suggest that the technology is promising for further reductions in loss and increases in bandwidth and operational frequency through additional structural optimization.