Design and Modeling for Nanomagnet Logic Circuits and Architectures

As a possible replacement or supplementary technology for Complimentary Metal- Oxide-Semiconductor (CMOS) technology, Nanomagnet Logic (NML) employs near- est neighbor dipole-dipole interactions for logic operations. NML has the benefits of low power consumption, non-volatility, radiation hardness, etc. To leverage the benefits of NML, the research in this dissertation has helped advance the state of the art of design and modeling of NML circuits and architectures. The work in this dissertation has shown that the integration of NML with CMOS is feasible through magnetic-electrical interface (MEI) designs based on magnetic tunnel junction. These MEI designs are especially important as hybrid NML and CMOS architectures are approached. As an extension from the MEI work, designs of magnetic content ad- dressable memory based on current induced domain wall motion are compact and energy efficient without sacrificing speed, overcoming a major challenge faced by content addressable memory designs. As much of NML studies need designs and simulations, an NML layout design methodology using energy states tackles the side effect of next nearest neighbor couplings in NML circuits, and a software package developed for assisting simulation is practical and effective for automating NML sim- ulation processes and saving time.