Synthesized WSe2 Field-Effect Transistors and Process for Steep Transistors

Doctoral Dissertation


Voltage scaling is an important factor in device miniaturization that leads to reduction in power consumption. Tunnel field-effect transistors (TFETs) are attractive candidates to overcome this fundamental limitation of the MOSFET. Atomically-thin two-dimensional semiconductors present new opportunities for minimizing transistor channel thickness and improving gate efficiency. The epitaxy of two-dimensional materials has been advanced in the past 5 years to enable device research to move from exfoliated to grown channels, from customized electron beam patterning to stepper lithography, from back gates to deposited top gate dielectrics, and from single device processes to full batch processes. The aim of this research has been to utilize synthesized WSe2, a transition metal dichalcogenide (TMD), as a FET channel material and to develop a TFET fabrication process. A stepper-based process has been demonstrated for fabricating WSe2-on-sapphire FETs with 3-4 monolayer channel thicknesses. The WSe2 was grown by collaborators from Penn State University by metal organic chemical vapor deposition (MOCVD). The development of a device process based on these materials has allowed wafer scale batch fabrication of 2D transistors for the first time and characterization of transport across centimeter scale sapphire substrates. This research has found solutions across a wide range of technical challenges. Methods for gate stack nucleation were developed to deposit gate dielectrics on WSe2 channels. The gate dielectric was nucleated using low temperature atomic layer deposition (ALD) of Al2O3 at 110° C to initiate layer formation, followed by Al2O3 at 200° C to complete the dielectric. The FET gate stacks were pinhole free yielding leakage current density of less than 0.1 fA/μm2 at 1 V and an equivalent oxide thickness (EOT) of 4.8 nm (physical thickness of 11 nm). In contrast to conventional semiconductor processing, contact adhesion is an important consideration. Contacts must generally be anchored to the substrate and the contacts themselves must not have inherent strain as this can then delaminate the 2D material. Methods for forming junctions and doping are also required. For this, electric double layer (EDL) doping of WSe2 channels has been utilized using polyethylene oxide: cesium perchlorate (PEO:CsClO4) and side gates. Use of these doping schemes required development of measurement protocols to establish measurement repeatability and enable the exploration of n-FETs, p-FETs and TFETs.


Attribute NameValues
Author Mina Asghari Heidarlou
Contributor Gregory Snider, Committee Member
Contributor Alan C. Seabaugh, Research Director
Contributor Susan Fullerton, Committee Member
Contributor Scott Howard, Committee Member
Degree Level Doctoral Dissertation
Degree Discipline Electrical Engineering
Degree Name Doctor of Philosophy
Banner Code
  • PHD-EE

Defense Date
  • 2019-07-01

Submission Date 2019-07-08
Record Visibility Public
Content License
  • All rights reserved

Departments and Units
Catalog Record


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