High-Performance Back-End-of-Line Compatible Indium Tungsten Oxide (IWO) Transistors for Monolithic-3D Application

Doctoral Dissertation
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Abstract

In the past decades, the demand for high-performance computing systems has arisen quickly due to the exponentially growing amount of data that needs to be processed daily. However, the performance improvement of computing systems is now facing two main challenges: 1) Moore’s law has slowed down as the tech node enters the single-digit era, and 2) the gap between the performance of processor and memory is growing by 30% every year, which leads to “the memory wall” problem.

Monolithic 3D integration is a promising approach to overcoming these two challenges. In the monolithic 3D integrated circuits (M3D-ICs), each layer of devices is directly built on top of the previous layers, and different layers are connected through the monolithic-interlayer-vias (MIVs). This approach can provide higher transistor density without scaling the transistor size and higher bandwidth due to its high-density MIVs.

This approach’s main challenge is forming a high-quality active layer on top of the isolation layer within the BEOL-compatible thermal budget (< 400 °C). The performance of most traditional semiconductor materials formed within this thermal budget is highly degraded due to their low crystallinity. Unlike conventional materials, amorphous oxide semiconductor (AOS) is a class of semiconductor materials that can maintain high mobility at the amorphous state because of their special band structure. This unique property makes it a strong candidate as the active layer material in M3D-ICs.

This dissertation mainly evaluated the capability of Indium Tungsten Oxide (IWO), a high-mobility AOS material, to be used as the channel material for high-performance BEOL-compatible transistors. It explored its potential applications in monolithic 3D integrated memory. To begin with, a BEOL-compatible back-gate and dual-gate process of IWO transistor with the high-k gate dielectric was developed. It demonstrated an ultra-scaled dual-gate IWO transistor with well-targeted VTH, excellent electrostatic control, and the highest drive current among all other enhancement-mode AOS transistors. In addition, an IWO-transistor-based 2T-capacitorless DRAM with a long retention time is proposed and experimentally demonstrated for the first time. Moreover, an IL-free IWO ferroelectric transistor, based on our first proposed W-sacrificial-layer process, was also demonstrated, which showed the highest memory window, endurance, and read/write speed, as compared to other AOS ferroelectric transistors.

Attributes

Attribute NameValues
Author Huacheng Ye
Contributor Suman Datta, Research Director
Contributor Gregory Snider, Committee Member
Contributor Christopher Hinkle, Committee Member
Contributor Ningyuan Cao, Research Director
Degree Level Doctoral Dissertation
Degree Discipline Electrical Engineering
Degree Name Doctor of Philosophy
Banner Code
  • PHD-EE

Defense Date
  • 2022-08-10

Submission Date 2022-12-06
Record Visibility Public
Content License
  • All rights reserved

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Digital Object Identifier

doi:10.7274/w0892805c44

This DOI is the best way to cite this doctoral dissertation.

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