Design, Fabrication and Modeling of Clocked Nanomagnet Logic Circuit Elements

Nanomagnet Logic (NML) devices hold great promises for low power, non-volatile logic. Magnetic Quantum-dot Cellular Automata (MQCA) based NML has been implemented for data paths and majority logic gates. However, the experimental demonstrations of NML circuits used large external magnetic fields. On-chip implementation of NML circuits will require a way of generating the magnetic fields inside the chip as well as selective control of the logic gates with local magnetic fields. Although current carrying wires can generate magnetic fields, it is not trivial to generate strong enough magnetic fields required for the excitation of prototype NML devices and gates. In this dissertation, a scheme of on-chip clocking of nanomagnets is presented with simulation studies that use Cu lines wrapped with magnetic materials from three sides. Cu lines that incorporate permalloy yokes and are capable of handling high current were designed and fabricated. Two different fabrication methods have been used to implement the clock lines. With proper design and material selection, magnetic fields were obtained that are strong enough to switch individual nanomagnets as well as NML gates and data paths, without using excessive current. A magnetic annealing furnace that can modify the magnetic characteristics of the clock lines in a way that facilitates nanomagnet switching was designed and built. The CMOS circuit necessary for driving the clock lines was designed, and the equivalent circuit model of the clock lines along with nanomagnets was developed, which helps to calculate the power dissipation and the frequency response of the overall NML circuit. Analytical models and a numerical simulator that can help to investigate nanomagnet switching dynamics under the influence of several physical effects, as well as facilitate the NML circuit design process were developed.